This invention relates to the manufacture of electronic device modules which include high-performance semiconductor devices (including CMOS logic devices, DRAM memory devices and the like) and interconnections between those devices. In particular, the invention relates to fabrication of high-density chip interconnections with improved reliability and reduced cost.
Electronic devices are continuing to become more complex with each generation, while at the same time their respective device elements are becoming smaller. This trend toward greater device density and complexity presents special challenges for the device packaging technologist. Semiconductor devices at present are manufactured with either wire bond pads or C4 pads to connect such devices to the next level interconnect; this is generally termed the first level of packaging.
The packaging sector has for a number of years represented the primary constraint on improving system speed for many semiconductor chip technologies. At the same time, the packaging of a device represents a high proportion of the total cost; recent cost modeling indicates that the cost of the packaging may account for as much as 80% of the total cost for leading edge devices.
An example of a complex, large-scale chip which presents a challenge for packaging technology is the system-on-a-chip (SOC) which includes multiple interconnected chips having different functions. A large SOC may be fabricated from separate processor or memory chips using a transfer and join (T&J) method in which chip-to-chip interconnections are made through a thin film to which multiple chips are bonded. An example of this methodology is shown in FIG. 1A. A thin film structure having interconnect wiring is fabricated on a glass wafer or plate. Chips 1 and 2, coated with thin films having wiring levels 1a and 2a respectively, are bonded to interconnect layer 20 using stud/via connections. In this example, studs 15 are formed on the interconnect layer and attach to the chips using solder connections 16. The studs are aligned to vias 11 formed in a layer 10 (typically polyimide) overlying the chips. The back sides of chips 1 and 2 are planarized and are coated with an adhesive layer 3, to which a backing wafer 4 is attached. The glass wafer or plate is removed from interconnect layer 20, leaving behind the interconnect wiring with the bonded chips. Electrical bonding pads 21 are formed on the chip-to-chip interconnect layer 20, and have C4 pads 22 formed thereon. Details of the T&J process are discussed in U.S. Pat. No. 6,444,560, the disclosure of which is incorporated herein by reference.
Chip-to-chip placements with the above-described T&J methodology may be as close as 25 μm to 60 μm, with a placement accuracy of about 1 μm. It is noteworthy that chips 1 and 2 may have different functions and be fabricated by different processes. The T&J method thus permits fabrication of a system-on-a-chip in which different devices are closely interconnected (see FIG. 1B).
The use of C4 pads or wirebond pads for connecting the SOC to a motherboard imposes practical limits on the wiring density and bandwidth of the packaged device, due to the spacing requirements of the pads (a typical C4 pitch is at least 150 μm, and generally ranges from 0.5 mm to 2.5 mm). Furthermore, each C4 connection represents a signal delay of about 50 psec.
It therefore is desirable to extend the above-described T&J methodology from a chip-to-chip interconnection scheme to a chip-to-package integration technology, in order to (1) permit more efficient packaging of high-density devices and (2) fabricate a device module with reduced cost.